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never stop thinking. microcontrollers data sheet, may 2000 c504 8-bit single-chip microcontroller
edition 2000-05 published by infineon technologies ag, st.-martin-strasse 53, d-81541 mnchen, germany ? infineon technologies ag 2000. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office in germany or our infineon technologies representatives worldwide (see address list). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
microcontrollers data sheet, may 2000 never stop thinking. c504 8-bit single-chip microcontroller
enhanced hooks technology tm is a trademark and patent of metalink corporation licensed to infineon technologies. c504 revision history: 2000-05 previous version: 1996-05 page subjects (major changes since last revision) 35 - 40 otp memory operation is added. 41 table on version byte content is added. 57 - 60 ac characteristics of programming mode is added. several v cc is replaced by v dd . several specification for sah-c504 is removed we listen to your comments any information within this document that you feel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com
data sheet 1 2000-05 c504 8-bit single-chip microcontroller c500 family c504 ? fully compatible to standard 8051 microcontroller ? up to 40 mhz external operating frequency ? 16 kbyte on-chip program memory C c504-2r: rom version (with optional rom protection) C c504-2e: programmable otp version C c504-l: without on-chip program memory ? 256 byte on-chip ram ?256 byte on-chip xram ? four 8-bit ports C 2 ports with mixed analog/digital i/o capability ? three 16-bit timers/counters C timer 2 with up/down counter feature further features are listed next page. figure 1 c504 functional units mcb02589 on-chip emulation support module port 0 port 1 port 2 port 3 ram 256 x 8 xram 256 x 8 c500 t0 t1 8-bit usart rom/otp 16 k x 8 oscillator watchdog 10-bit adc timer 2 10-bit compare unit 16-bit capture/compare unit watchdog timer i/o 4-bit analog inputs i/o 8-bit digital i/o 8-bit digital i/o 4-bit analog inputs core
c504 data sheet 2 2000-05 ? capture/compare unit for pwm signal generation and signal capturing C 3-channel, 16-bit capture/compare unit C 1-channel, 10-bit compare unit ? full duplex serial interface (usart) ? 10-bit a/d converter with 8 multiplexed inputs ? twelve interrupt sources with two priority levels ? on-chip emulation support logic (enhanced hooks technology tm ) ? programmable 15-bit watchdog timer ? oscillator watchdog ? fast power on reset ? power saving modes C idle mode C power-down mode with wake-up capability through int0 ? m-qfp-44 package ? temperature ranges: sab-c504 t a : 0 to 70 c SAF-C504 t a : C 40 to 85 c sak-c504 t a : C 40 to 125 c (max. operating frequency: 24 mhz) ordering information the ordering code for infineon technologies microcontrollers provides an exact reference to the required product. this ordering code indentifies: ? the derivative itself, i.e. its function set ? the specified temperature range ? the package and the type of delivery for the available ordering codes for the c504, please refer to the product information microcontrollers which summarizes all available microcontroller variants. note: the ordering codes for the mask-rom versions are defined for each product after verification of the respective rom code.
c504 data sheet 3 2000-05 figure 2 logic symbol mcl02590 dd vv ss v aref agnd v xtal1 xtal2 reset ea ale psen ctrap cout3 c504 port 0 8-bit digital i/o 8-bit digital i/o/ port 1 4-bit analog inputs port 2 8-bit digital i/o 4-bit analog inputs port 3 8-bit digital i/o/
c504 data sheet 4 2000-05 figure 3 pin configuration (top view) ea cout3 p0.6 / ad6 p0.7 / ad7 p0.5 / ad5 p2.6 / a14 p2.5 / a13 psen p2.7 / a15 ale p2.4 / a12 p2.3 / a11 xtal2 xtal1 ctrap p1.7 / cout2 p3.2 / an4 / int0 p3.3 / an5 / int1 reset p1.6 / cc2 p1.5 / cout1 11 16 34 39 44 16 21 22 c504-lm mcp02532 p2.2 / a10 p2.1 / a9 v v dd ss p2.0 / a8 33 31 30 29 28 27 26 25 24 23 32 p0.4 / ad4 p3.0 / rxd p3.4 / an6 / t0 p3.5 / an7 / t1 p3.1 / txd p1.4 / cc1 v v aref gnd 2345 78 10 9 20 19 18 17 15 14 13 12 43 42 41 40 38 37 36 35 c504-2rm p1.1 / an1 / t2ex p1.0 / an0 / t2 p1.3 / an3 / cout0 p1.2 / an2 / cc0 p0.3 / ad3 p0.2 / ad2 p0.1 / ad1 p0.0 / ad0 p3.7 / rd p3.6 / wr / int2 c504-2em
c504 data sheet 5 2000-05 table 1 pin definitions and functions symbol pin number (p-mqfp-44) i/o 1) function p1.0 - p1.7 40 - 44, 1 - 3 40 41 42 43 44 1 2 3 i/o port 1 is an 8-bit bidirectional port. port 1 pins can be used for digital input/output. p1.0 - p1.3 can also be used as analog inputs of the a/d converter. as secondary digital functions, port 1 contains the timer 2 pins and the capture/compare inputs/outputs. port 1 pins are assigned to be used as analog inputs via the register p1ana. the functions are assigned to the pins of port 1 as follows: p1.0 / an0 / t2 analog input channel 0 / input to timer 2 p1.1 / an1 / t2ex analog input channel 1 / capture/reload trigger of timer 2 up-down count p1.2 / an2 / cc0 analog input channel 2 / input/output of capture/ compare channel 0 p1.3 / an3 / cout0 analog input channel 3 / output of capture/compare channel 0 p1.4 / cc1 input/output of capture/ compare channel 1 p1.5 / cout1 output of capture/compare channel 1 p1.6 / cc2 input/output of capture/ compare channel 2 p1.7 / cout2 output of capture/compare channel 2 reset 4 i reset a high level on this pin for two machine cycles while the oscillator is running resets the device. an internal diffused resistor to v ss permits power-on reset using only an external capacitor to v dd .
c504 data sheet 6 2000-05 p3.0 - p3.7 5, 7 - 13 5 7 8 9 10 11 12 13 i/o port 3 is an 8-bit bidirectional port. p3.0 (r d) and p3.1 (t d) operate as defined for the c501. p3.2 to p3.7 contain the external interrupt inputs, timer inputs, and four of the analog inputs of the a/d converter. port 3 pins are assigned to be used as analog inputs via the bits of sfr p3ana. p3.6/wr can be assigned as a third interrupt input. the functions are assigned to the pins of port 3 as follows: p3.0 / rxd receiver data input (asynch.) or data input/output (synch.) of serial interface p3.1 / txd transmitter data output (asynch.) or clock output (synch.) of serial interface p3.2 / an4 / int0 analog input channel 4 / external interrupt 0 input / timer 0 gate control input p3.3 / an5 / int1 analog input channel 5 / external interrupt 1 input / timer 1 gate control input p3.4 / an6 / t0 analog input channel 6 / timer 0 counter input p3.5 / an7 / t1 analog input channel 7 / timer 1 counter input p3.6 / wr / int2 wr control output; latches the data byte from port 0 into the external data memory / external interrupt 2 input p3.7 / rd rd control output; enables the external data memory table 1 pin definitions and functions (contd) symbol pin number (p-mqfp-44) i/o 1) function
c504 data sheet 7 2000-05 ctrap 6i ccu trap input with ctrap = low, the compare outputs of the capcom unit are switched to the logic level as defined in the coini register (if they are enabled by the bits in sfr trcon). ctrap is an input pin with an internal pullup resistor. for power saving reasons, the signal source which drives the ctrap input should be at high or floating level during power-down mode. xtal2 14 C xtal2 output of the inverting oscillator amplifier. xtal1 15 C xtal1 input to the inverting oscillator amplifier and input to the internal clock generator circuits. to drive the device from an external clock source, xtal1 should be driven, while xtal2 is left unconnected. there are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is divided down by a divide-by-two flip-flop. minimum and maximum high and low times as well as rise/fall times specified in the ac characteristics must be observed. p2.0 - p2.7 18-25 i/o port 2 is a bidirectional i/o port with internal pullup resistors. port 2 pins that have 1s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. as inputs, port 2 pins being externally pulled low will source current ( i il , in the dc characteristics) because of the internal pullup resistors. port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (movx @dptr). in this application it uses strong internal pullup resistors when issuing 1s. during accesses to external data memory that use 8-bit addresses (movx @ri), port 2 issues the contents of the p2 special function register. table 1 pin definitions and functions (contd) symbol pin number (p-mqfp-44) i/o 1) function
c504 data sheet 8 2000-05 psen 26 o the program store enable output is a control signal that enables the external program memory to the bus during external fetch operations. it is activated every six oscillator periods except during external data memory accesses. remains high during internal program execution. ale 27 o the address latch enable output is used for latching the low-byte of the address into external memory during normal operation. it is activated every six oscillator periods except during an external data memory access. when instructions are executed from internal rom (ea = 1) the ale generation can be disabled by clearing bit eale in sfr syscon. cout3 28 o 10-bit compare channel output this pin is used for the output signal of the 10-bit compare timer 2 unit. cout3 can be disabled and set to a high or low state. ea 29 i external access enable when held at high level, instructions are fetched from the internal rom (c504-2r only) when the pc is less than 4000 h . when held at low level, the c504 fetches all instructions from external program memory. for the c504-l, this pin must be tied low. p0.0 - p0.7 37 - 30 i/o port 0 is an 8-bit open-drain bidirectional i/o port. port 0 pins that have 1s written to them float; and in that state, can be used as high-impedance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external program or data memory. in this application, it uses strong internal pullup resistors when issuing 1 s. port 0 also outputs the code bytes during program verification in the c504-2r. external pullup resistors are required during program (rom) verification. v aref 38 C reference voltage for the a/d converter. table 1 pin definitions and functions (contd) symbol pin number (p-mqfp-44) i/o 1) function
c504 data sheet 9 2000-05 v agnd 39 C reference ground for the a/d converter. v ss 16 C ground (0 v) v dd 17 C power supply (+ 5 v) 1) i = input, o = output table 1 pin definitions and functions (contd) symbol pin number (p-mqfp-44) i/o 1) function
c504 data sheet 10 2000-05 figure 4 block diagram of the c504 mcb02591 oscillator watchdog osc & timing cpu timer 1 timer 2 interrupt unit usart capture/compare unit a/d converter 10-bit timer 0 s & h mux xram 256 x 8 ram rom/otp 16 k x 8 port 0 port 1 port 2 port 3 port 0 port 1 port 2 port 3 xtal2 xtal1 v dd ss v reset ale psen ea cout3 ctrap v agnd aref v 8-bit digital i/o 4-bit analog inputs 8-bit digital i/o 8-bit digital i/o 4-bit analog inputs 8-bit digital i/o support emulation logic 256 x 8
c504 data sheet 11 2000-05 cpu the c504 is efficient both as a controller and as an arithmetic processor. it has extensive facilities for binary and bcd arithmetic and excels in its bit-handling capabilities. efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. with a 12 mhz crystal, 58% of the instructions are executed in 1.0 m s ( 24 mhz: 500 ns, 40 mhz: 300 ns). special function register psw (address d0 h ) reset value: 00 h bit function cy carry flag used by arithmetic instructions. ac auxiliary carry flag used by instructions which execute bcd operations. f0 general purpose flag 0 rs1 rs0 register bank select control bits these bits are used to select one of the four register banks. ov overflow flag used by arithmetic instruction. f1 general purpose flag 1 p parity flag set/cleared by hardware after each instruction to indicate an odd/ even number of one bits in the accumulator. cy ac f0 rs1 rs0 ov f1 p d0 h psw d7 h d6 h d5 h d4 h d3 h d2 h d1 h d0 h bit no. msb lsb rs1 rs0 function 0 0 bank 0 selected, data address 00 h -07 h 0 1 bank 1 selected, data address 08 h -0f h 1 0 bank 2 selected, data address 10 h -17 h 1 1 bank 3 selected, data address 18 h -1f h
c504 data sheet 12 2000-05 memory organization the c504 cpu manipulates operands in the following four address spaces: C up to 64 kbyte of program memory: 16k rom for c504-2r 16k otp for c504-2e C up to 64 kbyte of external data memory C 256 bytes of internal data memory C 256 bytes of internal xram data memory C a 128 byte special function register area figure 5 illustrates the memory address spaces of the c504. figure 5 c504 memory map mcd02592 00 h h 7f 0000 h 3fff h external ffff h h 4000 (ea = 0) (ea = 1) "code space" "data space" "internal data space" h 0000 h ffff external ff00 h feff h internal xram ram internal internal external internal ram ff h h 80 function special register direct address 80 h h ff address indirect
c504 data sheet 13 2000-05 reset and system clock operation the reset input is an active high input. an internal schmitt trigger is used at the input for noise rejection. since the reset is synchronized internally, the reset pin must be held high for at least two machine cycles (24 oscillator periods) while the oscillator is running. during reset, pins ale and psen are configured as inputs and should not be stimulated externally. (an external stimulation at these lines during reset activates several test modes which are reserved for test purposes. this, in turn, may cause unpredictable output operations at several port pins). at the reset pin, a pulldown resistor is internally connected to v ss to allow a power-up reset with an external capacitor only. an automatic reset can be obtained when v dd is applied by connecting the reset pin to v dd via a capacitor. after v dd has been turned on, the capacitor must hold the voltage level at the reset pin for a specific time to effect a complete reset. the time required for a reset operation is the oscillator start-up time and the time for 2 machine cycles, which must be at least 10 - 20 ms, under normal conditions. this requirement is typically met using a capacitor of 4.7 to 10 m f. the same considerations apply if the reset signal is generated externally ( figure 6b ). in each case, it must be assured that the oscillator has started up properly and that at least two machine cycles have passed before the reset signal goes inactive. figure 6 shows the possible reset circuitries. figure 6 reset circuitries a) + b) + c504 reset c) & mcs03352 c504 c504 reset reset
c504 data sheet 14 2000-05 figure 7 shows the recommended oscillator circuit for the c504, while figure 8 shows the circuit for using an external clock source. figure 7 recommended oscillator circuit figure 8 external clock source mcs03353 c 3.5 - 40 mhz xtal2 xtal1 c = 20 pf 10 pf for crystal operation c504 c mcs03355 xtal1 xtal2 n.c. v dd c504 external clock signal
c504 data sheet 15 2000-05 enhanced hooks emulation concept the enhanced hooks emulation concept of the c500 microcontroller family is a new, innovative way to control the execution of c500 mcus and to gain extensive information on the internal operation of the controllers. emulation of on-chip rom based programs is possible, too. each production chip has built-in logic for the support of the enhanced hooks emulation concept. therefore, no costly bond-out chips are necessary for emulation. this also ensure that emulation and production chips are identical. the enhanced hooks technology tm , which requires embedded logic in the c500 allows the c500 together with an eh-ic to function similar to a bond-out chip. this simplifies the design and reduces costs of an ice-system. ice-systems using an eh-ic and a compatible c500 are able to emulate all operating modes of the different versions of the c500. this includes emulation of rom, rom with code rollover and romless modes of operation. it is also able to operate in single step mode and to read the sfrs after a break. figure 9 basic c500 mcu enhanced hooks concept configuration port 0, port 2 and some of the control lines of the c500 based mcu are used by enhanced hooks emulation concept to control the operation of the device during emulation and to transfer informations about the program execution and data transfer between the external emulation hardware (ice-system) and the c500 mcu. mcs02647 syscon pcon tcon reset ea psen ale port 0 port 2 i/o ports optional port 3 port 1 c500 mcu interface circuit enhanced hooks rport 0 rport 2 rtcon rpcon rsyscon tea tale tpsen eh-ic target system interface ice-system interface to emulation hardware
c504 data sheet 16 2000-05 special function registers all registers, except the program counter and the four general purpose register banks, reside in the special function register area. the 63 special function registers (sfr) include pointers and registers that provide an interface between the cpu and the other on-chip peripherals. all sfrs with addresses where address bits 0-2 are 0 (e.g. 80 h , 88 h , 90 h , 98 h , , f0 h , f8 h ) are bit-addressable. the sfrs of the c504 are listed in table 2 and table 3 . in table 2, they are organized in groups which refer to the functional blocks of the c504. table 3 illustrates the contents of the sfrs in numeric order of their addresses.
c504 data sheet 17 2000-05 table 2 special function registers - functional blocks block symbol name addr. contents after reset cpu acc b dph dpl psw sp syscon accumulator b-register data pointer, high byte data pointer, low byte program status word register stack pointer system control register e0 h 1) f0 h 1) 83 h 82 h d0 h 1) 81 h b1 h 00 h 00 h 00 h 00 h 00 h 07 h xx10xxx0 b 3) interrupt system ien0 ien1 ccie 2) ip0 ip1 itcon interrupt enable register 0 interrupt enable register 1 capture/compare interrupt enable reg. interrupt priority register 0 interrupt priority register 1 interrupt trigger condition register a8 h 1) a9 h d6 h b8 h 1) b9 h 9a h 0x000000 b 3) xx000000 b 3) 00 h xx000000 b 3) xx000000 b 3) 00101010 b ports p0 p1 p1ana 2) p2 p3 p3ana 2) port 0 port 1 port 1 analog input selection register port 2 port 3 port 3 analog input selection register 80 h 1) 90 h 1) 90 h 1) 4) a0 h 1) b0 h 1) b0 h 1) 4) ff h ff h xxxx1111 b 3) ff h ff h xx1111xx b 3) a/d- converter adcon0 adcon1 addath addatl p1ana 2) p3ana 2) a/d converter control register 0 a/d converter control register 1 a/d converter data register high byte a/d converter data register low byte port 1 analog input selection register port 3 analog input selection register d8 h 1) dc h d9 h da h 90 h 1) 4) b0 h 1) 4) xx000000 b 3) 01xxx000 b 3) 00 h 00xxxxxx b 3) xxxx1111 b 3) xx1111xx b 3) serial channels pcon 2) sbuf scon power control register serial channel buffer register serial channel control register 87 h 99 h 98 h 1) 000x0000 b xx h 3) 00 h timer 0/ timer 1 tcon th0 th1 tl0 tl1 tmod timer 0/1 control register timer 0, high byte timer 1, high byte timer 0, low byte timer 1, low byte timer mode register 88 h 1) 8c h 8d h 8a h 8b h 89 h 00 h 00 h 00 h 00 h 00 h 00 h 1) bit-addressable special function registers 2) this special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) x means that the value is undefined and the location is reserved 4) sfr is located in the mapped sfr area. for accessing this sfr, bit rmap in sfr syscon must be set.
c504 data sheet 18 2000-05 timer 2 t2con t2mod rc2h rc2l th2 tl2 timer 2 control register timer 2 mode register timer 2 reload capture register, high byte timer 2 reload capture register, low byte timer 2 high byte timer 2 low byte c8 h 1) c9 h cb h ca h cd h cc h 00 h xxxxxxx0 b 3) 00 h 00 h 00 h 00 h capture / compare unit ct1con ccpl ccph ct1ofl ct1ofh cmsel0 cmsel1 coini trcon ccl0 cch0 ccl1 cch1 ccl2 cch2 ccir ccie 2) ct2con cp2l cp2h cmp2l cmp2h bcon compare timer 1 control register compare timer 1 period register, low byte compare timer 1 period register, high byte compare timer 1 offset register, low byte compare timer 1 offset register, high byte capture/compare mode select register 0 capture/compare mode select register 1 compare output initialization register trap enable control register capture/compare register 0, low byte capture/compare register 0, high byte capture/compare register 1, low byte capture/compare register 1, high byte capture/compare register 2, low byte capture/compare register 2, high byte capture/compare interrupt request flag reg. capture/compare interrupt enable register compare timer 2 control register compare timer 2 period register, low byte compare timer 2 period register, high byte compare timer 2 compare register, low byte compare timer 2 compare register, high byte block commutation control register e1 h de h df h e6 h e7 h e3 h e4 h e2 h cf h c2 h c3 h c4 h c5 h c6 h c7 h e5 h d6 h c1 h d2 h d3 h d4 h d5 h d7 h 00010000 b 00 h 00 h 00 h 00 h 00 h 00 h ff h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00010000 b 00 h xxxxxx00 b 3) 00 h xxxxxx00 b 3) 00 h watchdog timer wdcon wdtrel watchdog timer control register watchdog timer reload register c0 h 1) 86 h xxxx0000 b 3) 00 h power saving mode pcon 2) pcon1 power control register power control register 1 87 h 88 h 1) 4) 000x0000 b 3) 0xxxxxxx b 3) 1) bit-addressable special function registers 2) this special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) x means that the value is undefined and the location is reserved 4) sfr is located in the mapped sfr area. for accessing this sfr, bit rmap in sfr syscon must be set. table 2 special function registers - functional blocks (contd) block symbol name addr. contents after reset
c504 data sheet 19 2000-05 table 3 contents of the sfrs, sfrs in numeric order of their addresses addr register content after reset 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 80 h 2) p0 ff h .7 .6 .5 .4 .3 .2 .1 .0 81 h sp 07 h .7 .6 .5 .4 .3 .2 .1 .0 82 h dpl 00 h .7 .6 .5 .4 .3 .2 .1 .0 83 h dph 00 h .7 .6 .5 .4 .3 .2 .1 .0 86 h wdtrel 00 h wdt psel .6 .5 .4 .3 .2 .1 .0 87 h pcon 000x- 0000 b smod pds idls C gf1 gf0 pde idle 88 h 2) tcon 00 h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 88 h 1)3) pcon1 0xxx- xxxx b ewpd C C C C C C C 89 h tmod 00 h gate c/t m1 m0 gate c/t m1 m0 8a h tl0 00 h .7 .6 .5 .4 .3 .2 .1 .0 8b h tl1 00 h .7 .6 .5 .4 .3 .2 .1 .0 8c h th0 00 h .7 .6 .5 .4 .3 .2 .1 .0 8d h th1 00 h .7 .6 .5 .4 .3 .2 .1 .0 90 h 2) p1 ff h .7 .6 .5 .4 .3 .2 t2ex t2 90 h 2)3) p1ana xxxx- 1111 b C C C C ean3 ean2 ean1 ean0 98 h 2) scon 00 h sm0 sm1 sm2 ren tb8 rb8 ti ri 99 h sbuf xx h .7 .6 .5 .4 .3 .2 .1 .0 9a h itcon 0010- 1010 b it2 ie2 i2etf i2etr i1etf i1etr i0etf i0etr a0 h 2) p2 ff h .7 .6 .5 .4 .3 .2 .1 .0 a8 h 2) ien0 0x00- 0000 b ea C et2 es et1 ex1 et0 ex0 a9 h ien1 xx00- 0000 b C C ect1 eccm ect2 ecem ex2 eadc 1) x means that the value is undefined and the location is reserved 2) bit-addressable special function registers 3) sfr is located in the mapped sfr area. for accessing this sfr, bit rmap in sfr syscon must be set.
c504 data sheet 20 2000-05 b0 h 2) p3 ff h rd wr t1 t0 int1 int0 txd rxd b0 h 2)3) p3ana xx11- 11xx b C C ean7 ean6 ean5 ean4 C C b1 h syscon xx10- xxx0 b CCealermapCCCxmap b8 h 2) ip0 xx00- 0000 b C C pt2 ps pt1 px1 pt0 px0 b9 h ip1 xx00- 0000 b C C pct1 pccm pct2 pcem px2 padc c0 h 2) wdcon xxxx- 0000 b C C C C owds wdts wdt swdt c1 h ct2con 0001- 0000 b ct2p ect2o ste2 ct2 res ct2r clk2 clk1 clk0 c2 h ccl0 00 h .7 .6 .5 .4 .3 .2 .1 .0 c3 h cch0 00 h .7 .6 .5 .4 .3 .2 .1 .0 c4 h ccl1 00 h .7 .6 .5 .4 .3 .2 .1 .0 c5 h cch1 00 h .7 .6 .5 .4 .3 .2 .1 .0 c6 h ccl2 00 h .7 .6 .5 .4 .3 .2 .1 .0 c7 h cch2 00 h .7 .6 .5 .4 .3 .2 .1 .0 c8 h 2) t2con 00 h tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/ rl2 c9 h t2mod xxxx- xxx0 b CCCCCCCdcen ca h rc2l 00 h .7 .6 .5 .4 .3 .2 .1 .0 cb h rc2h 00 h .7 .6 .5 .4 .3 .2 .1 .0 cc h tl2 00 h .7 .6 .5 .4 .3 .2 .1 .0 cd h th2 00 h .7 .6 .5 .4 .3 .2 .1 .0 cf h trcon 00 h trpen trf tren5 tren4 tren3 tren2 tren1 tren0 1) x means that the value is undefined and the location is reserved 2) bit-addressable special function registers 3) sfr is located in the mapped sfr area. for accessing this sfr, bit rmap in sfr syscon must be set. table 3 contents of the sfrs, sfrs in numeric order of their addresses (contd) addr register content after reset 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
c504 data sheet 21 2000-05 d0 h 2) psw 00 h cy ac f0 rs1 rs0 ov f1 p d2 h cp2l 00 h .7 .6 .5 .4 .3 .2 .1 .0 d3 h cp2h xxxx. xx00 b CCCCCC.1.0 d4 h cmp2l 00 h .7 .6 .5 .4 .3 .2 .1 .0 d5 h cmp2h xxxx. xx00 b CCCCCC.1.0 d6 h ccie 00 h ectp ectc cc2 fen cc2 ren cc1 fen cc1 ren cc0 fen cc0 ren d7 h bcon 00 h bcmp bcem pwm1 pwm0 ebce bcerr bcen bcm1 bcm0 d8 h 2) adcon0 xx00- 0000 b C C iadc bsy adm mx2 mx1 mx0 d9 h addath 00 h .9 .8 .7 .6 .5 .4 .3 .2 da h addatl 00xx- xxxx b .1.0CCCCCC dc h adcon1 01xx- x000 b adcl1 adcl0 C C C mx2 mx1 mx0 de h ccpl 00 h .7 .6 .5 .4 .3 .2 .1 .0 df h ccph 00 h .7 .6 .5 .4 .3 .2 .1 .0 e0 h 2) acc 00 h .7 .6 .5 .4 .3 .2 .1 .0 e1 h ct1con 0001- 0000 b ctm etrp ste1 ct1 res ct1r clk2 clk1 clk0 e2 h coini ff h cout 3i coutx i cout 2i cc2i cout 1i cc1i cout 0i cc0i e3 h cmsel0 00 h cmsel 13 cmsel 12 cmsel 11 cmsel 10 cmsel 03 cmsel 02 cmsel 01 cmsel 00 e4 h cmsel1 00 h 0000cmsel 23 cmsel 22 cmsel 21 cmsel 20 e5 h ccir 00 h ct1fp ct1fc cc2f cc2r cc1f cc1r cc0f cc0r e6 h ct1ofl 00 h .7 .6 .5 .4 .3 .2 .1 .0 e7 h ct1ofh 00 h .7 .6 .5 .4 .3 .2 .1 .0 f0 h 2) b 00 h .7 .6 .5 .4 .3 .2 .1 .0 1) x means that the value is undefined and the location is reserved 2) bit-addressable special function registers table 3 contents of the sfrs, sfrs in numeric order of their addresses (contd) addr register content after reset 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
c504 data sheet 22 2000-05 timer/counter 0 and 1 timer/counter 0 and 1 can be used in four operating modes as listed in table 4 . in the timer function (c/ t = 0), the register is incremented every machine cycle. therefore the count rate is f osc /12. in the counter function the register is incremented in response to a 1-to-0 transition at its corresponding external input pin (p3.4/t0, p3.5/t1). since it takes two machine cycles to detect a falling edge the max. count rate is f osc /24. external inputs int0 and int1 (p3.2, p3.3) can be programmed to function as a gate to facilitate pulse width measurements. figure 10 illustrates the input clock logic. figure 10 timer/counter 0 and 1 input clock logic table 4 timer/counter 0 and 1 operating modes mode description tmod input clock gate c/ t m1 m0 internal external (max.) 0 8-bit timer/counter with a divide-by-32 prescaler xx00 f osc /12 32 f osc /24 32 1 16-bit timer/counter x x 1 1 f osc /12 f osc /24 2 8-bit timer/counter with 8-bit auto-reload xx00 f osc /12 f osc /24 3 timer/counter 0 used as one 8-bit timer/counter and one 8-bit timer timer 1 stops xx11 f osc /12 f osc /24 12 f osc /12 mcs01768 osc f c/t tmod 0 control timer 0/1 input clock tcon tr 0/1 gate tmod & =1 1 p3.4/t0 p3.5/t1 max p3.2/int0 p3.3/int1 osc /24 f 1 _ <
c504 data sheet 23 2000-05 timer/counter 2 timer 2 is a 16-bit timer/counter with an up/down count feature. it can operate either as a timer or as an event counter. this is selected by bit c/ t2 of sfr t2con. it has three operating modes as shown in table 5 . note: = falling edge table 5 timer/counter 2 operating modes mode t2con t2mod dcen t2con exen p1.1/ t2ex remarks input clock r clk or t clk cp/ rl2 tr2 internal external (p1.0/t2) 16-bit auto- reload 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 1 x x x 0 1 reload upon overflow reload trigger (falling edge) down counting up counting f osc /12 max f osc /24 16-bit cap- ture 0 0 1 1 1 1 x x 0 1 x 16 bit timer/ counter (only up-counting) capture th2, tl2 ? rc2h, rc2l f osc /12 max f osc /24 baud rate gene- rator 1 1 x x 1 1 x x 0 1 x no overflow interrupt request (tf2) extra external interrupt (timer 2) f osc /2 max f osc /24 off x x 0 x x x timer 2 stops C C
c504 data sheet 24 2000-05 capture/compare unit the capture/compare unit (ccu) of the c504 consists of a 16-bit 3-channel capture/ compare unit (capcom) and a 10-bit 1-channel compare unit (comp). in compare mode, the capcom unit provides two output signals per channel, which can have inverted signal polarity and non-overlapping pulse transitions. the comp unit can generate a single pwm output signal and is further used to modulate the capcom output signals. in capture mode, the value of the compare timer 1 is stored in the capture registers if a signal transition occurs at the pins ccx. figure 11 shows the block diagram of the ccu. figure 11 block diagram of the ccu
c504 data sheet 25 2000-05 the compare timers 1 and 2 are free running, processor clock coupled 16-bit / 10-bit timers; each of which has a count rate with a maximum of f osc /2 up to f osc /256. the compare timer operations with its possible compare output signal waveforms are shown in figure 12 . figure 12 basic operating modes of the capcom unit compare timer 1 can be programmed for both operating modes while compare timer 2 works only in operating mode 0 with one output signal of selectable polarity at the pin cout3. period value value compare 0000 h cc cout value compare value period offset off t value compare 0000 h value period compare value offset value period off t coini=0 coini=1 off t : interrupts can be generated mct03356 compare timer 1 in operating mode 0 a) standard pwm (edge aligned) compare timer 1 in operating mode 1 b) standard pwm (single edge aligned) with programmable dead time ( ) off t symetrical pwm (center aligned) c) with programmable dead time ( ) symetrical pwm (center aligned) d) off t cc cout coini=0 coini=1 cc cout cc cout
c504 data sheet 26 2000-05 serial interface (usart) the serial port is full duplex and can operate in four modes (one synchronous mode, three asynchronous modes) as illustrated in table 6 . the possible baud rates can be calculated using the formulas given in table 6 . figure 13 baud rate generation for the serial interface table 6 usart operating modes mode scon baud rate description sm0 sm1 000 f osc /12 serial data enters and exits through r d. t d outputs the shift clock. 8-bit are transmitted/received (lsb first) 1 0 1 timer 1/2 overflow rate 8-bit uart 10 bits are transmitted (through t d) or received (r d) 210 f osc /32 or f osc /64 9-bit uart 11 bits are transmitted (t d) or received (r d) 3 1 1 timer 1/2 overflow rate 9-bit uart like mode 2 except the variable baud rate 2 sm0 / sm1 pcon.7 (smod) (rclk, tclk) t2con timer 1 overflow phase 2 clk (= /2) f osc timer 2 overflow mode 1, 3 mode 2 00 11 mcb02414 baud rate clock
c504 data sheet 27 2000-05 the possible baud rates can be calculated using the formulas given in table 7 . table 7 formulas for calculating baud rates source of baud rate operating mode baud rate oscillator 0 2 f osc /12 (2 smod f osc )/64 timer 1 (16-bit timer) (8-bit timer with 8-bit auto-reload) 1, 3 1, 3 (2 smod timer 1 overflow rate)/32 (2 smod f osc )/(32 12 (256-th1)) timer 2 1, 3 f osc /(32 (65536-(rc2h, rc2l))
c504 data sheet 28 2000-05 10-bit a/d converter the c504 has a high performance 8-channel 10-bit a/d converter using successive approximation technique for the conversion of analog input voltages. figure 14 shows the block diagram of the a/d converter. figure 14 a/d converter block diagram addatl addath shaded bit locations are not used in adc-functions. aref agnd v v osc f /2 32, 16, 8, 4 prescaler clock port 1/3 conversion write to addatl mcb02616 bus internal continuous single/ a/d converter in input clock conversion clock f adc f mux s & h mode lsb .8 start of msb .1 .6 .7 .4 .5 .2 .3 (d9 ) h - - - - - - h (da ) ien1 (a9 ) adcon0 (d8 ) adcl1 adcon1 (dc ) p3ana (b0 ) p1ana (90 ) - - - - h bsy - iadc h adm mx2 ean6 adcl0 h - - ean7 h - - ean5 -- mx2 ean4 ean3 - ean2 mx1 mx0 mx1 - mx0 - ean0 ean1 eccm - h ect1 ect2 ecem eadc ex2 bus internal
c504 data sheet 29 2000-05 the a/d converter uses two clock signals for operation: the conversion clock f adc (= 1/ t adc ) and the input clock f in (= 1/ t in ). both clock signals are derived from the c504 system clock f osc which is applied at the xtal pins. the duration of an a/d conversion is a multiple of the period of the f in clock signal. the table in figure 15 shows the prescaler ratios and the resulting a/d conversion times which must be selected for typical system clock rates. figure 15 a/d converter clock selection the analog inputs are located at port 1 and port 3 (4 lines on each port). the corresponding port 1 and port 3 pins have a port structure, which allows the pins to be used either as digital i/os or analog inputs. the analog input function of these mixed digital/analog port lines is selected via the registers p1ana and p3ana. mcu system clock rate ( f osc ) f in [mhz] prescaler f adc [mhz] a/d conversion time [ m s] ratio adcl1 adcl0 3.5 mhz 1.75 ? 4 0 0 .438 48 t in = 27.4 12 mhz 6 ? 4 0 0 1.5 48 t in = 8 16 mhz 8 ? 40 0 2 48 t in = 6 24 mhz 12 ? 8 0 1 1.5 96 t in = 8 32 mhz 16 ? 80 1 2 96 t in = 6 40 mhz 20 ? 16 1 0 1.25 192 t in = 9.6
c504 data sheet 30 2000-05 interrupt system the c504 provides 12 interrupt sources with two priority levels. figures 16 and 17 give a general overview of the interrupt sources and illustrate the interrupt request and control flags. figure 16 interrupt request sources (part 1)
c504 data sheet 31 2000-05 figure 17 interrupt request sources (part 2) mcb02596 itcon.7 it2 p3.6/wr/int2 itcon.4 itcon.5 1 ex2 ie2 ien1.1 itcon.6 004b h low priority high priority ip1.1 px2 cc0r cc0ren ccie0.0 1 ccir.0 ccir.1 ccie0.1 cc0fen cc0f cc1f cc1fen ccie0.3 ccir.3 ccir.2 ccie0.2 cc1ren cc1r cc2f cc2fen ccie0.5 ccir.5 ccir.4 ccie0.4 cc2ren cc2r pccm ip1.4 h 0063 ien1.4 eccm ccir.7 ccie.7 ct1fp ectp ectc ct1fc ccie.6 ccir.6 1 ect1 ien1.5 006b h ip1.5 pct1 pct2 ip1.3 h 005b ien1.3 ect2 ct2p ct2con.7 pcem ip1.2 h 0053 ien1.2 ecem 1 bcon.3 bcerr ebce etrp trf ct1con.6 trcon.6 bcon.4 ea p1.2/an2/cc0 p1.4/cc1 p1.6/cc2 capture/compare match interrupt compare timer 1 interrupt interrupt compare timer 2 interrupt ccu emergency bit addressable request flag is cleared by hardware ien0.7 _ < < _ < _ _ <
c504 data sheet 32 2000-05 a low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low-priority interrupt. a high-priority interrupt cannot be interrupted by any other interrupt sources. if two requests of different priority level are received simultaneously, the request of higher priority is serviced. if requests of the same priority are received simultaneously, an internal polling sequence determines which request is serviced. thus within each priority level there is a second priority structure determined by the polling sequence as shown in table 9 . table 8 interrupt vector addresses request flags interrupt source vector address ie0 tf0 ie1 tf1 ri + ti tf2 + exf2 iadc ie2 trf, bcerr ct2p cc0f-cc2f, cc0r-cc2r ct1fp, ct1fc C external interrupt 0 timer 0 interrupt external interrupt 1 timer 1 interrupt serial port interrupt timer 2 interrupt a/d converter interrupt external interrupt 2 capcom emergency interrupt compare timer 2 interrupt capture/compare match interrupt compare timer 1 interrupt power-down interrupt 0003 h 000b h 0013 h 001b h 0023 h 002b h 0043 h 004b h 0053 h 005b h 0063 h 006b h 007b h table 9 interrupt source structure interrupt source priority external interrupt 0 timer 0 interrupt external interrupt 1 timer 1 interrupt serial channel timer 2 interrupt a/d converter external interrupt 2 ccu emergency interrupt compare timer 2 interrupt capture/compare match interrupt compare timer 1 interrupt high low high priority low priority
c504 data sheet 33 2000-05 fail save mechanisms the c504 offers enhanced fail save mechanisms, which allow an automatic recovery from software or hardware failure. C a programmable 15-bit watchdog timer C oscillator watchdog programmable watchdog timer the watchdog timer in the c504 is a 15-bit timer, which is incremented by a count rate of either f cycle /2 or f cycle /32 ( f cycle = f osc /12). only the upper 7 bits of the 15-bit watchdog timer count value can be programmed. figure 18 shows the block diagram of the programmable watchdog timer. figure 18 block diagram of the programmable watchdog timer the watchdog timer can be started by software (bit swdt in sfr wdcon), but it cannot be stopped during active mode of the device. if the software fails to refresh the running watchdog timer, an internal reset will be initiated. the reset cause (external reset or reset caused by the watchdog) can be examined by software (status flag wdts in sfr wdcon is set). a refresh of the watchdog timer is done by setting bits wdt and swdt (both in sfr wdcon) consecutively. this double instruction sequence has been implemented to increase system security. it must be noted, however, that the watchdog timer is halted during the idle mode and power down mode of the processor.
c504 data sheet 34 2000-05 oscillator watchdog the oscillator watchdog of the c504 serves for three functions: C monitoring of the on-chip oscillator's function the watchdog supervises the on-chip oscillator's frequency; if it is lower than the frequency of an auxiliary rc oscillator, the internal clock is supplied by this rc oscillator and the c504 is brought into reset. if the failure condition disappears, the c504 executes a final reset phase of typically 1 ms in order to allow the oscillator to stabilize; then, the oscillator watchdog reset is released and the part starts program execution again. C fast internal reset after power-on the oscillator watchdog unit provides a clock supply for the reset before the on-chip oscillator has started. the oscillator watchdog unit also works identically to the monitoring function. C control of external wake-up from software power-down mode when the software power-down mode is terminated by a low level at pin p3.2/int0 , the oscillator watchdog unit ensures that the microcontroller resumes operation (execution of the power-down wake-up interrupt) with the nominal clock rate. in the power-down mode, the rc oscillator and the on-chip oscillator are stopped. both oscillators are started again when power-down mode is released. when the on-chip oscillator has a higher frequency than the rc oscillator, the microcontroller starts operation after a final delay of typically 1 ms in order to allow the on-chip oscillator to stabilize.
c504 data sheet 35 2000-05 figure 19 block diagram of the oscillator watchdog power saving modes the c504 provides two power saving modes, the idle mode and the power down mode. C in the idle mode , the oscillator of the c504 continues to run, but the cpu is gated off from the clock signal. however, the interrupt system, the serial port, the a/d converter, and all timers with the exception of the watchdog timer, are further provided with the clock. the cpu status is preserved in its entirety: the stack pointer, program counter, program status word, accumulator, and all other registers maintain their data during idle mode. C in the power down mode, the rc oscillator and the on-chip oscillator which operates with the xtal pins are both stopped. therefore all functions of the microcontroller are stopped and only the contents of the on-chip ram, xram and the sfrs are maintained. the port pins, which are controlled by their port latches, output the values that are held by their sfrs. table 10 gives a general overview of the entry and exit procedures of the power saving modes.
c504 data sheet 36 2000-05 if a power saving mode is terminated through an interrupt, including the external wake- up via p3.2/int0 , the microcontroller state (cpu, ports, peripherals) remains preserved. if it is terminated by a hardware reset, the microcontroller is reset to its default state. in the power down mode of operation, v dd can be reduced to minimize power consumption. it must be ensured, however, that v dd is not reduced before the power down mode is invoked, and that v dd is restored to its normal operating level, before the power down mode is terminated. table 10 power saving modes overview mode entering (2-instruction example) leaving by remarks idle mode orl pcon, #01h orl pcon, #20h occurrence of any enabled interrupt cpu clock is stopped; cpu maintains their data; peripheral units are active (if enabled) and provided with clock. hardware reset power down mode with external wake-up capability from power down enabled orl syscon,#10h orl pcon1,#80h anl syscon,#0efh orl pcon,#02h orl pcon,#40h hardware reset oscillator is stopped; contents of on-chip ram and sfrs are maintained. p3.2/int0 goes low for at least 10 m s. it is desired that the pin be held at high level during the power down mode entry and up to the wake-up. with external wake-up capability from power down disabled orl pcon,#02h orl pcon,#40h hardware reset
c504 data sheet 37 2000-05 otp memory operation (c504-2e only) the c504-2e is the otp version of the c504 microcontroller with a 16kbyte one-time programmable (otp) program memory. fast programming cycles are achieved (1 byte in 100 m s) with the c504-2e. several levels of otp memory protection can be selected as well. to program the device, the c504-2e must be put into the programming mode. typically, this is not done in-system, but in a special programming hardware. in the programming mode, the c504-2e operates as a slave device similar to an eprom standalone memory device and must be controlled with address/data information, control lines, and an external 11.5 v programming voltage. figure 20 shows the pins of the c504-2e which are required for controlling of the otp programming mode. figure 20 c504-2e programming mode configuration pmsel1 pmsel0 xtal2 xtal1 p0.0 - 7 v ss v dd c504-2e mcs03360 p2.0 - 7 pale ea / prog prd reset psen psel v pp port 2 port 0
c504 data sheet 38 2000-05 pin configuration in programming mode figure 21 pin configuration of the c504-2e in programming mode (top view) ea / n.c. d6 d7 d5 a6 a5 / a13 psen a7 prog a4 / a12 a3 / a11 xtal2 xtal1 n.c. prd reset n.c. n.c. 11 16 34 39 44 16 21 22 mcp03361 a2 / a10 a1 / a9 v v dd ss a0 / a8 33 31 30 29 28 27 26 25 24 23 32 d4 pmsel0 pale n.c. psel 2345 78 10 9 20 19 18 17 15 14 13 12 43 42 41 40 38 37 36 35 c504-2e d3 d2 d1 d0 n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. pmsel1 v pp
c504 data sheet 39 2000-05 pin definitions table 11 contains the functional description of all c504-2e pins which are required for otp memory programming. table 11 pin definitions and functions of the c504-2e in programming mode symbol pin no. i/o function p-mqfp-44 reset 4 i reset this input must be at static 1 (active) level throughout the entire programming mode. pmsel0 pmsel1 5 7 i i programming mode selection pins these pins are used to select the different access modes in programming mode. pmsel1,0 must satisfy a setup time to the rising edge of pale. when the logic level of pmsel1,0 is changed, pale must be at low level. psel 8i basic programming mode select this input is used for the basic programming mode selection and must be switched according to figure 22 . prd 9i programming mode read strobe this input is used for read access control for otp memory read, version byte read, and lock bit read operations. pale 10 i programming address latch enable pale is used to latch the high address lines. the high address lines must satisfy a setup and hold time to/from the falling edge of pale. pale must be at low level when the logic level of pmsel1,0 is changed. xtal2 14 o xtal2 output of the inverting oscillator amplifier. pmsel1 pmsel0 access mode 00reserved 0 1 read version bytes 1 0 program/read lock bits 1 1 program/read otp memory byte
c504 data sheet 40 2000-05 xtal1 15 i xtal1 input to the oscillator amplifier. v ss 16 C ground (0 v) must be applied in programming mode. v dd 17 C power supply (+ 5 v) must be applied in programming mode. p2.0 - p2.7 18 - 25 i address lines p2.0 - p2.7 are used as multiplexed address input lines a0 - a7 and a8 - a13. a8 - a13 must be latched with pale. psen 26 i program store enable this input must be at static 0 level during the whole programming mode. prog 27 i programming mode write strobe this input is used in programming mode as a write strobe for otp memory program and lock bit write operations. during basic programming mode selection, a low level must be applied to prog . ea / v pp 29 C programming voltage this pin must be held at 11.5 v ( v pp ) during programming of an otp memory byte or lock bit. during an otp memory read operation, this pin must be at v ih . this pin is also used for basic programming mode selection. for basic programming mode selection, a low level must be applied. p0.7 - p0.0 30-37 i/o data lines in programming mode, data bytes are transferred via the bidirectional d7 - d0 data lines which are located at port 0. n.c. 1-3, 6, 11-13, 28, 38-44 C not connected these pins should not be connected in programming mode. table 11 pin definitions and functions of the c504-2e in programming mode (contd) symbol pin no. i/o function p-mqfp-44
c504 data sheet 41 2000-05 programming mode selection the selection for the otp programming mode can be separated into two different parts: C basic programming mode selection C access mode selection with basic programming mode selection, the device is put into the mode in which it is possible to access the otp memory through the programming interface logic. further, after selection of the basic programming mode, otp memory accesses are executed by using one of the access modes. these access modes are otp memory byte program/ read, version byte read, and program/read lock byte operations. the basic programming mode selection scheme is shown in figure 22 . figure 22 basic programming mode selection mct03362 v dd 5 v clock (xtal1/ xtal2) reset "1" psen "0" pmsel1,0 prog prd "1" "0" 0,1 psel pale "0" ea/ v pp v pp v ih 0 v ready for access mode selection during this period signals are not actively driven stable
c504 data sheet 42 2000-05 lock bits programming / read the c504-2e has two programmable lock bits which, when programmed according to table 13 , provide four levels of protection for the on-chip otp code memory. note: a 1 means that the lock bit is unprogrammed; a 0 means that lock bit is programmed. table 12 access modes selection access mode ea / v pp prog prd pmsel address (port 2) data (port 0) 10 program otp memory byte v pp h h h a0 - a7 a8 - a15 d0 - d7 read otp memory byte v ih h program otp lock bits v pp hhl Cd1,d0 see table 13 read otp lock bits v ih h read otp version byte v ih h l h byte addr. of version byte d0 - d7 table 13 lock bit protection types lock bits protection level protection type d1 d0 1 1 level 0 the otp lock feature is disabled. during normal operation of the c504-2e, the state of the ea pin is not latched on reset. 1 0 level 1 during normal operation of the c504-2e, movc instructions executed from external program memory are disabled from fetching code bytes from internal memory. ea is sampled and latched on reset. an otp memory read operation is only possible according to rom/otp verification mode 2. further programming of the otp memory is disabled (reprogramming security). 0 1 level 2 same as level 1, but also otp memory read operation using rom verification mode 2 is disabled. 0 0 level 3 same as level 2; but additionally external code execution by setting ea = low during normal operation of the c504-2e is no more possible. external code execution, which is initiated by an internal program (e.g. by an internal jump instruction above the rom boundary), is still possible.
c504 data sheet 43 2000-05 version bytes the c504-2e and c504-2r provide three version bytes at mapped address locations fc h , fd h , and fe h . the information stored in the version bytes, is defined by the mask of each microcontroller step. therefore, the version bytes can be read but not written. the three version bytes hold information as manufacturer code, device type, and stepping code. the steppings of the c504 contain the following version byte information: future steppings of the c504 will typically have a different value for version byte 2. table 14 content of version bytes stepping version byte 0, vr0 (mapped addr. fc h ) version byte 1, vr1 (mapped addr. fd h ) version byte 2, vr2 (mapped addr. fe h ) c504-2r ac-step c5 h 04 h 01 h c504-2e es-aa-step c5 h 84 h 01 h c504-2e es-bb-step c5 h 84 h 04 h c504-2e ca-step c5 h 84 h 09 h
c504 data sheet 44 2000-05 note: stresses above those listed under absolute maximum ratings may cause permanent damage of the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for longer periods may affect device reliability. during absolute maximum rating overload conditions ( v in > v dd or v in < v ss ) the voltage on v dd pins with respect to ground ( v ss ) must not exceed the values defined by the absolute maximum ratings. absolute maximum ratings parameter symbol limit values unit notes min. max. storage temperature t st C65 150 cC voltage on v dd pins with respect to ground ( v ss ) v dd C0.5 6.5 v C voltage on any pin with respect to ground ( v ss ) v in C0.5 v dd + 0.5 v C input current on any pin during overload condition C C 10 10 ma C absolute sum of all input currents during overload condition C C |100 ma| ma C power dissipation p diss C1 wC operating conditions parameter symbol limit values unit notes min. max. supply voltage v dd 4.25 5.5 v C ground voltage v ss 0vC ambient temperature sab-c504 SAF-C504 sak-c504 t a t a t a 0 C40 C40 70 85 125 cC analog reference voltage v aref 4 v dd + 0.1 v C analog ground voltage v agnd v ss C0.1 v ss + 0.2 v C analog input voltage v ain v agnd v aref vC cpu clock f cpu 1.75 20 mhz C
c504 data sheet 45 2000-05 parameter interpretation the parameters listed in the following partly represent the characteristics of the c504 and partly its demands on the system. to aid in interpreting the parameters right, when evaluating them for a design, they are marked in column symbol: cc ( c ontroller c haracteristics): the logic of the c504 will provide signals with the respective characteristics. sr ( s ystem requirement): the external system must provide signals with the respective characteristics to the c504. dc characteristics (operating conditions apply) parameter symbol limit values unit test condition min. max. input low voltage (except ea , reset, ctrap ) v il sr C 0.5 0.2 v dd C 0.1 vC input low voltage (ea ) v il1 sr C 0.5 0.2 v dd C 0.3 vC input low voltage (reset, ctrap ) v il2 sr C 0.5 0.2 v dd + 0.1 vC input high voltage (except xtal1, reset and ctrap ) v ih sr 0.2 v dd + 0.9 v dd + 0.5 v 11) input high voltage to xtal1 v ih1 sr 0.7 v dd v dd + 0.5 v C input high voltage to reset and ctrap v ih2 sr 0.6 v dd v dd + 0.5 v C output low voltage (ports 1, 2, 3, cout3) v ol cc C 0.45 v i ol =1.6 ma 1) output low voltage (port 0, ale, psen ) v ol1 cc C 0.45 v i ol =3.2 ma 1) output high voltage (ports 1, 2, 3) v oh cc 2.4 0.9 v dd C C v i oh =C80 m a i oh =C10 m a output high voltage (ports 1, 3 pins in push-pull mode and cout3) v oh1 cc 0.9 v dd Cv i oh =C800 m a
c504 data sheet 46 2000-05 output high voltage (port 0 in external bus mode, ale, psen ) v oh2 cc 2.4 0.9 v dd C C v i oh =C800 m a 2) i oh =C80 m a 2) logic 0 input current (ports 1, 2, 3) i il sr C 10 C 50 m a v in =0.45v logical 1-to-0 transition current (ports 1, 2, 3) i tl sr C 65 C 650 m a v in =2v input leakage current (port 0, ea ) i li cc C 1 m a0.45< v in < v dd pin capacitance c io cc C 10 pf f c = 1 mhz, t a =25 c overload current i ov sr C 5ma 7) 8) programming voltage (c504-2e) v pp sr 10.9 12.1 v 11.5 v 5% 10) power supply current parameter sym- bol limit values unit test condition typ. 8) max. 9) active mode c504-2r 24 mhz 40 mhz i dd i dd 27.4 43.1 35.9 57.2 ma ma 4) c504-2e 24 mhz 40 mhz i dd i dd 20.9 31.0 27.9 41.5 ma ma idle mode c504-2r 24 mhz 40 mhz i dd i dd 14.6 22.4 19.3 31.3 ma ma 5) c504-2e 24 mhz 40 mhz i dd i dd 12.3 16.1 16.1 20.9 ma ma power-down mode c504-2r i pd 130 m a v dd =2 ? 5.5 v 3) c504-2e i pd 35 60 m a at ea / v pp in prog. mode c504-2e i ddp C30maC dc characteristics (contd) (operating conditions apply) parameter symbol limit values unit test condition min. max.
c504 data sheet 47 2000-05 notes: 1) capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the v ol of ale and port 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation. in the worst case (capacitive loading > 100 pf), the noise pulse on ale line may exceed 0.8 v. in such cases, it may be desirable to qualify ale with a schmitt-trigger, or use an address latch with a schmitt-trigger strobe input. 2) capacitive loading on ports 0 and 2 may cause the v oh on ale and psen to momentarily fall below the 0.9 v dd specification when the address lines are stabilizing. 3) i pd (power-down mode) is measured under following conditions: ea =port 0= v dd ; reset = v ss ; xtal2 = n.c.; xtal1 = v ss ; v agnd = v ss ; all other pins are disconnected. 4) i dd (active mode) is measured with: xtal1 driven with t clch , t chcl = 5 ns, v il = v ss +0.5v, v ih = v dd C 0.5 v; xtal2 = n.c.; ea = port 0 = port 1 = reset = v dd ; all other pins are disconnected. i dd would be slightly higher if a crystal oscillator is used (appr. 1 ma). 5) i dd (idle mode) is measured with all output pins disconnected and with all peripherals disabled; xtal1 driven with t clch , t chcl = 5 ns, v il = v ss +0.5v, v ih = v dd C 0.5 v; xtal2 = n.c.; reset = ea = v ss ; port 0 = v dd ; all other pins are disconnected; 6) overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range (i.e. v ov > v dd + 0.5 v or v ov < v ss C 0.5 v). the supply voltage v dd and v ss must remain within the specified limits. the absolute sum of input currents on all port pins may not exceed 50 ma. 7) not 100 % tested, guaranteed by design characterization. 8) the typical i dd values are periodically measured at t a = + 25 c and v dd = 5 v but not 100% tested. 9) the maximum i dd values are measured under worst case conditions ( t a = 0c or C40c and v dd =5.5v) 10)this v pp specification is valid for devices with version byte 2 = 02h or higher. devices with version byte 2 = 01h must be programmed with v pp =12v 5%. 11)for the c504-2e es-aa-step the v ih min. for ea is 0.8 v dd .
c504 data sheet 48 2000-05 figure 23 idd diagram dd i 0 0 osc f mcd03368 mhz 40 ma active mode idle mode dd max i dd typ i 5 10152025 10 20 30 40 50 60 30 35 active mode idle mode c504-2e dd i 0 0 osc f mcd03367 mhz 40 ma active mode dd max i dd typ i 5 10152025 10 20 30 40 50 60 30 35 idle mode c504-2r active mode idle mode
c504 data sheet 49 2000-05 note: f osc is the oscillator frequency in mhz. i dd values are given in ma. notes see next page. power supply current calculation formulas parameter symbol formula active mode c504-2r i dd typ i dd max 0.98 f osc + 3.9 1.33 f osc + 4.0 c504-2e i dd typ i dd max 0.63 f osc + 5.75 0.85 f osc + 7.5 idle mode c504-2r i dd typ i dd max 0.51 f osc + 2.35 0.75 f osc + 1.3 c504-2e i dd typ i dd max 0.24 f osc + 6.5 0.30 f osc + 8.86 a/d converter characteristics (operating conditions apply) parameter symbol limit values unit test condition min. max. analog input voltage v ain sr v agnd v aref v 1) sample time t s cc C64 t in 32 t in 16 t in 8 t in ns prescaler ? 32 prescaler ? 16 prescaler ? 8 prescaler ? 4 2) conversion cycle time t adcc cc C 384 t in 192 t in 96 t in 48 t in ns prescaler ? 32 prescaler ? 16 prescaler ? 8 prescaler ? 4 3) total unadjusted error t ue cc C 2lsb v ss + 0.5 v v in v dd C0.5v 4) C 4lsb v ss < v in < v ss + 0.5 v v dd C0.5v < v in < v dd 4) internal resistance of reference voltage source r aref sr C t adc /250 C 0.25 k w t adc in [ns] 5) 6) internal resistance of analog source r asrc sr C t s /500 C 0.25 k w t s in [ns] 2) 6) adc input capacitance c ain cc C 50 pf 6)
c504 data sheet 50 2000-05 further timing conditions: t adc min = 500 ns t in = 2/ f osc = 2 t clcl notes: 1) v ain may exceed v agnd or v aref up to the absolute maximum ratings. however, the conversion result in these cases will be x000 h or x3ff h , respectively. 2) during the sample time, the input capacitance c ain can be charged/discharged by the external source. the internal resistance of the analog source must allow the capacitance to reach their final voltage level within t s . after the end of the sample time t s , changes of the analog input voltage have no effect on the conversion result. 3) this parameter includes the sample time t s , the time for determining the digital result and the time for the calibration. values for the conversion clock t adc depend on programming and can be taken from the table on the previous page. 4) t ue is tested at v aref = 5.0 v, v agnd = 0 v, v dd = 4.9 v. it is guaranteed by design characterization for all other voltages within the defined voltage range. if an overload condition occurs on maximum 2 not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 ma, an additional conversion error of 1/2 lsb is permissible. 5) during the conversion, the adcs capacitance must be repeatedly charged or discharged. the internal resistance of the reference source must allow the capacitance to reach their final voltage level within the indicated time. the maximum internal resistance results from the programmed conversion timing. 6) not 100% tested, but guaranteed by design characterization. clock calculation table clock prescaler ratio adcl1, 0 t adc t s t adcc ? 32 1 1 32 t in 64 t in 384 t in ? 16 1 0 16 t in 32 t in 192 t in ? 8018 t in 16 t in 96 t in ? 4004 t in 8 t in 48 t in
c504 data sheet 51 2000-05 notes: 1) interfacing the c504 to devices with float times up to 75 ns is permissible. this limited bus contention will not cause any damage to port 0 drivers. ac characteristics for c504-l / c504-2r / c504-2e (operating conditions apply) ( c l for port 0, ale and psen outputs = 100 pf; c l for all other outputs = 80 pf) parameter symbol limit values unit 12-mhz clock variable clock 1/ t clcl = 3.5 mhz to 12 mhz min. max. min. max. program memory characteristics ale pulse width t lhll cc 127 C2 t clcl C40 C ns address setup to ale t avll cc 43 C t clcl C40 C ns address hold after ale t llax cc 30 C t clcl C23 C ns ale low to valid instr in t lliv sr C 233 C 4 t clcl C100 ns ale to psen t llpl cc 58 C t clcl C25 C ns psen pulse width t plph cc 215 C 3 t clcl C35 C ns psen to valid instr in t pliv sr C 150 C 3 t clcl C100 ns input instruction hold after psen t pxix sr0C0 C ns input instruction float after psen t pxiz 1) sr C 63 C t clcl C20 ns address valid after psen t pxav 1) cc 75 C t clcl C8 C ns address to valid instr in t aviv sr C 302 C 5 t clcl C115 ns address float to psen t azpl cc0C0 C ns
c504 data sheet 52 2000-05 ac characteristics for c504-l / c504-2r / c504-2e (contd) parameter symbol limit values unit 12-mhz clock variable clock 1/ t clcl = 3.5 mhz to 12 mhz min. max. min. max. external data memory characteristics rd pulse width t rlrh cc 400 C 6 t clcl C100 C ns wr pulse width t wlwh cc 400 C 6 t clcl C100 C ns address hold after ale t llax2 cc 114 C 2 t clcl C53 C ns rd to valid data in t rldv sr C 252 C 5 t clcl C165 ns data hold after rd t rhdx sr 0 C 0 C ns data float after rd t rhdz sr C 97 C 2 t clcl C70 ns ale to valid data in t lldv sr C 517 C 8 t clcl C150 ns address to valid data in t avdv sr C 585 C 9 t clcl C165 ns ale to wr or rd t llwl cc 200 300 3 t clcl C50 3 t clcl +50 ns address valid to wr or rd t avwl cc 203 C 4 t clcl C130 C ns wr or rd high to ale high t whlh cc 43 123 t clcl C40 t clcl +40 ns data valid to wr transition t qvwx cc 33 C t clcl C50 C ns data setup before wr t qvwh cc 433 C 7 t clcl C150 C ns data hold after wr t whqx cc 33 C t clcl C50 C ns address float after rd t rlaz cc C 0 C 0 ns external clock drive characteristics parameter symbol limit values unit variable clock freq. = 3.5 mhz to 12 mhz min. max. oscillator period t clcl sr 83.3 294 ns high time t chcx sr 20 t clcl C t clcx ns low time t clcx sr 20 t clcl C t chcx ns rise time t clch sr C 20 ns fall time t chcl sr C 20 ns
c504 data sheet 53 2000-05 notes: 1) interfacing the c504 to devices with float times up to 37 ns is permissible. this limited bus contention will not cause any damage to port 0 drivers. ac characteristics for c504-l24 / c504-2r24 / c504-2e24 (operating conditions apply) ( c l for port 0, ale and psen outputs = 100 pf; c l for all other outputs = 80 pf) parameter symbol limit values unit 24-mhz clock variable clock 1/ t clcl = 3.5 mhz to 24 mhz min. max. min. max. program memory characteristics ale pulse width t lhll cc 43 C2 t clcl C40 C ns address setup to ale t avll cc 17 C t clcl C25 C ns address hold after ale t llax cc 17 C t clcl C25 C ns ale low to valid instr in t lliv sr C 80 C 4 t clcl C87 ns ale to psen t llpl cc 22 C t clcl C20 C ns psen pulse width t plph cc 95 C 3 t clcl C30 C ns psen to valid instr in t pliv sr C 60 C 3 t clcl C65 ns input instruction hold after psen t pxix sr 0 C 0 C ns input instruction float after psen t pxiz 1) sr C 32 C t clcl C10 ns address valid after psen t pxav 1) cc 37 C t clcl C5 C ns address to valid instr in t aviv sr C 148 C 5 t clcl C60 ns address float to psen t azpl cc 0 C 0 C ns
c504 data sheet 54 2000-05 ac characteristics for c504-l24 / c504-2r24 / c504-2e24 (contd) parameter symbol limit values unit 24-mhz clock variable clock 1/ t clcl = 3.5 mhz to 24 mhz min. max. min. max. external data memory characteristics rd pulse width t rlrh cc 180 C 6 t clcl C70 C ns wr pulse width t wlwh cc 180 C 6 t clcl C70 C ns address hold after ale t llax2 cc 56 C 2 t clcl C27 C ns rd to valid data in t rldv sr C 118 C 5 t clcl C90 ns data hold after rd t rhdx sr 0 C 0 C ns data float after rd t rhdz sr C 63 C 2 t clcl C20 ns ale to valid data in t lldv sr C 200 C 8 t clcl C133 ns address to valid data in t avdv sr C 220 C 9 t clcl C155 ns ale to wr or rd t llwl cc 75 175 3 t clcl C50 3 t clcl +50 ns address valid to wr t avwl cc 67 C 4 t clcl C97 C ns wr or rd high to ale high t whlh cc 17 67 t clcl C25 t clcl +25 ns data valid to wr transition t qvwx cc 5 C t clcl C37 C ns data setup before wr t qvwh cc 170 C 7 t clcl C122 C ns data hold after wr t whqx cc 15 C t clcl C27 C ns address float after rd t rlaz cc C 0 C 0 ns external clock drive parameter symbol limit values unit variable clock freq. = 3.5 mhz to 24 mhz min. max. oscillator period t clcl sr 41.7 294 ns high time t chcx sr 12 t clcl C t clcx ns low time t clcx sr 12 t clcl C t chcx ns rise time t clch sr C 12 ns fall time t chcl sr C 12 ns
c504 data sheet 55 2000-05 notes: 1) sak-c504 is not specified for 40 mhz operation. 2) interfacing the c504 to devices with float times up to 25 ns is permissible. this limited bus contention will not cause any damage to port 0 drivers. characteristics for c504-l40 / c504-2r40 / c504-2e40 (operating conditions apply) 1) ( c l for port 0, ale and psen outputs = 100 pf; c l for all other outputs = 80 pf) parameter symbol limit values unit 40-mhz clock variable clock 1/ t clcl = 3.5 mhz to 40 mhz min. max. min. max. program memory characteristics ale pulse width t lhll cc 35 C2 t clcl C15 C ns address setup to ale t avll cc 10 C t clcl C15 C ns address hold after ale t llax cc 10 C t clcl C15 C ns ale low to valid instr in t lliv sr C 55 C 4 t clcl C45 ns ale to psen t llpl cc 10 C t clcl C15 C ns psen pulse width t plph cc 60 C 3 t clcl C15 C ns psen to valid instr in t pliv sr C 25 C 3 t clcl C50 ns input instruction hold after psen t pxix sr 0 C 0 C ns input instruction float after psen t pxiz 2) sr C 20 C t clcl C5 ns address valid after psen t pxav 2) cc 20 C t clcl C5 C ns address to valid instr in t aviv sr C 65 C 5 t clcl C60 ns address float to psen t azpl cc C 5 C C 5 C ns ac
c504 data sheet 56 2000-05 ac characteristics for c504-l40 / c504-2r40 / c504-2e40 (contd) parameter symbol limit values unit 40-mhz clock variable clock 1/ t clcl = 3.5 mhz to 40 mhz min. max. min. max. external data memory characteristics rd pulse width t rlrh cc 120 C 6 t clcl C30 C ns wr pulse width t wlwh cc 120 C 6 t clcl C30 C ns address hold after ale t llax2 cc 35 C 2 t clcl C15 C ns rd to valid data in t rldv sr C 75 C 5 t clcl C50 ns data hold after rd t rhdx sr00Cns data float after rd t rhdz sr C 38 C 2 t clcl C12 ns ale to valid data in t lldv sr C 150 C 8 t clcl C50 ns address to valid data in t avdv sr C 150 C 9 t clcl C75 ns ale to wr or rd t llwl cc 60 90 3 t clcl C15 3 t clcl +15 ns address valid to wr t avwl cc 70 C 4 t clcl C30 C ns wr or rd high to ale high t whlh cc 10 40 t clcl C15 t clcl +15 ns data valid to wr transition t qvwx cc 5 C t clcl C20 C ns data setup before wr t qvwh cc 125 C 7 t clcl C50 C ns data hold after wr t whqx cc 5 C t clcl C20 C ns address float after rd t rlaz ccC0C0ns external clock drive parameter symbol limit values unit variable clock freq. = 3.5 mhz to 40 mhz min. max. oscillator period t clcl sr 25 294 ns high time t chcx sr 10 t clcl C t clcx ns low time t clcx sr 10 t clcl C t chcx ns rise time t clch sr C 10 ns fall time t chcl sr C 10 ns
c504 data sheet 57 2000-05 figure 24 program memory read cycle figure 25 data memory read cycle mct00096 ale psen port 2 lhll t a8 - a15 a8 - a15 a0 - a7 instr.in a0 - a7 port 0 t avll plph t t llpl t lliv t pliv t azpl t llax t pxiz t pxix t aviv t pxav mct00097 ale psen port 2 whlh t port 0 rd t lldv t rlrh t llwl t rldv t avll t llax2 t rlaz t avwl t avdv t rhdx t rhdz a0 - a7 from ri or dpl from pcl a0 - a7 instr. in data in a8 - a15 from pch p2.0 - p2.7 or a8 - a15 from dph
c504 data sheet 58 2000-05 figure 26 data memory write cycle figure 27 external clock cycle mct00098 ale psen port 2 whlh t port 0 wr t wlwh t llwl t qvwx t avll t llax2 t qvwh t avwl t whqx a0 - a7 from ri or dpl from pcl a0 - a7 instr.in data out a8 - a15 from pch p2.0 - p2.7 or a8 - a15 from dph mct00033 t chcx t clcx chcl t clch t v dd t clcl - 0.5v 0.45v dd 0.7 v v - 0.1 dd 0.2
c504 data sheet 59 2000-05 note: v pp = 11.5 v 5% is valid for devices with version byte 2 = 02 h or higher. devices with version byte 2 = 01 h must be programmed with v pp = 12 v 5%. ac characteristics of programming mode ( v dd = 5 v 10%; v pp = 11.5 v 5%; t a = 25 c 10 c) parameter symbol limit values unit min. max. pale pulse width t paw 35 Cns pmsel setup to pale rising edge t pms 10 C ns address setup to pale, prog , or prd falling edge t pas 10 C ns address hold after pale, prog , or prd falling edge t pah 10 C ns address, data setup to prog or prd t pcs 100 C ns address, data hold after prog or prd t pch 0Cns pmsel setup to prog or prd t pms 10 C ns pmsel hold after prog or prd t pmh 10 C ns prog pulse width t pww 100 C m s prd pulse width t prw 100 C ns address to valid data out t pad C75ns prd to valid data out t prd C20ns data hold after prd t pdh 0Cns data float after prd t pdf C20ns prog high between two consecutive prog low pulses t pwh1 1C m s prd high between two consecutive prd low pulses t pwh2 100 C ns xtal clock period t clkp 83.3 285.7 ns
c504 data sheet 60 2000-05 figure 28 programming code byte - write cycle timing t paw t pms pah t pas t a8-a13 a0-a7 d0-d7 pcs t pww t pch t t pwh mct03369 h, h pale pmsel1,0 port 2 port 0 prog note: prd must be high during a programming read cycle
c504 data sheet 61 2000-05 figure 29 verify code byte - read cycle timing t paw t pms pah t pas t a8-a13 a0-a7 pad t d0-d7 t pdh t pdf prd t pcs t prw t pch t t pwh mct03370 h, h pale pmsel1,0 port 2 port 0 prd note: prog must be high during a programming read cycle
c504 data sheet 62 2000-05 figure 30 lock bit access timing figure 31 version byte read timing h, l h, l d0, d1 d0, d1 t pcs pms t pmh t t pch pww t pms t prd t t pdh pdf t pmh t prw t pmsel1,0 port 0 prog prd note : pale should be low during a lock bit read / write cycle mct03371 e. g. fd d0-7 t pcs pms t t pdh pdf t pmh t mct03372 port 2 port 0 prd pmsel1,0 l, h h prw t prd t pch t note : prog must be high during a programming read cycle
c504 data sheet 63 2000-05 figure 32 rom verification mode 1 rom/otp verification characteristics for c504-2r / c504-2e rom verification mode 1 (c504-2r only) parameter symbol limit values unit min. max. address to valid data t avqv C 10 t clcl ns p1.0 - p1.7 p2.0 - p2.5 port 0 address data out address: p1.0 - p1.7 = a0 - a7 p2.0 - p2.5 = a8 - a13 data: p0.0 - p0.7 = d0 - d7 inputs: p2.6, p2.7, psen = ale, ea = reset = v ss v ih v ih2 avqv t mct03428
c504 data sheet 64 2000-05 figure 33 rom verification mode 2 rom/otp verification mode 2 parameter symbol limit values unit min. typ max. ale pulse width t awd C2 t clcl Cns ale period t acy C12 t clcl Cns data valid after ale t dva CC4 t clcl ns data stable after ale t dsa 8 t clcl CCns p3.5 setup to ale low t as C t clcl Cns oscillator frequency 1/ t clcl 4C6mhz mct02613 t acy t awd t dsa dva t t as data valid ale port 0 p3.5
c504 data sheet 65 2000-05 figure 34 ac testing: input, output waveforms figure 35 ac testing: float waveforms figure 36 recommended oscillator circuits for crystal oscillator ac inputs during testing are driven at v dd C 0.5 v for a logic 1 and 0.45 v for a logic 0. timing measurements are made at v ihmin for a logic 1 and v ilmax for a logic 0. 0.45 v v dd 0.2 -0.1 +0.9 0.2 dd v test points mct00039 v dd -0.5 v for timing purposes a port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loaded v oh / v ol level occurs. i ol / i oh 3 20 ma mct00038 v load v load -0.1 v +0.1 v load v timing reference points v oh -0.1 v +0.1 v ol v
c504 data sheet 66 2000-05 package information gpm05622 p-mqfp-44 (smd) (plastic metric quad flat package) sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm smd = surface mounted device
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